1. Field of the Invention
The present invention relates to an array substrate and a method of manufacturing the array substrate. More particularly, the present invention relates to an array substrate capable of reducing defects induced by static electricity generated during manufacturing process, and a method of manufacturing the array substrate.
2. Description of the Related Art
A liquid crystal display panel typically includes an array substrate, an upper substrate facing the array substrate, and a liquid crystal layer disposed between the array substrate and the upper substrate, where the array substrate includes a pixel region and a signal applying region. The pixel region includes a source line that extends in a first direction, a gate line that extends in a second direction that is substantially perpendicular to the first direction, and a pixel electrode that is electrically connected to the source line through a switching device. The signal applying region includes a first driving chip pad upon which a data driving chip that applies a data signal to the source line is mounted, and a second driving chip pad upon which a gate driving chip that applies a gate signal to the gate line is mounted.
When the array substrate is completely formed, a wiring test for inspecting electrical conditions of conductive lines formed on the array substrate is performed and then the array substrate is combined with the upper substrate such that a liquid crystal layer is disposed between the array substrate and the upper substrate. Then, a visual inspection (referred to as V/I) process for inspecting electrical and optical conditions of a display panel is performed.
Test lines and test pads for the wiring test process and the V/I process are respectively disposed along scribe lines of a mother board including a plurality of array substrates. In detail, the wiring test pad is disposed on outside regions of the scribe lines (or outside regions of the array substrate), while the V/I pad is disposed on an inside region of the scribe lines (or edge portions of the array substrate). The wiring test lines and V/I lines are disposed on the inside region of the scribe lines. The wiring test lines and the V/I lines are commonly used.
The V/I is performed by the V/I lines and the V/I pad disposed on the inside scribe line region, after the wiring test process is carried out and the array substrate is cut along the scribe line of the mother substrate. In the wiring test and V/I process, the gate lines and the source lines are grouped by certain units (for example, 2G2D or 2G3D) and tested by applying test signals.
According to a widely used wiring test, even numbered gate lines and odd numbered gate lines are grouped, respectively and the even numbered gate line group and the odd numbered gate line group are connected to different static current discharging wirings from each other, and test-signal is applied to each of the even numbered gate line group and the odd numbered gate line group. Additionally, even numbered source lines and odd numbered source lines are grouped, respectively, and the even numbered source line group and the odd numbered source line group are connected to separate static current discharge wires from each other, and a test signal is applied to each of the even numbered source line group and the source numbered gate line group.
The odd numbered gate lines and even numbered gate lines alternate with each other, so that each of the odd numbered gate lines is adjacent to each of the even numbered gate lines, so that an electrical short defect may be detected between the odd numbered gate lines and the even numbered gate lines. Therefore, the even numbered gate lines are grouped and the odd numbered lines are grouped. The same process described above may also be applied to the V/I process.